Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
A certain amount of supply current during a power-up of an integrated circuit is used to ensure proper initialization. The actual current consumed depends on the power-up ramp rate of the power supply used. Additionally, one or more supply voltages may first have to pass through their power-on reset threshold voltage level or levels for an integrated circuit to properly power up. An example of such a threshold voltage level may be a supply voltage rise-time limit, such as from initiation of a power-on reset condition, including a power-up condition. From the time of initiation of a power-on reset, power-on reset threshold voltage level or levels are to be at least met for a supply voltage or supply voltages, respectively, within a rise-time window.
A manufacturer of an integrated circuit may specify particular minimum supply currents and a maximum supply voltage level rise time in order for a customer to select a power supply meeting those specifications. To reduce cost of power supplies needed for use of an integrated circuit, power-on reset circuits may trip relatively late within a supply voltage rise-time window and still properly initialize the integrated circuit. However, with the scaling down in size of integrated circuits, there has been a commensurate reduction in supply voltage level. This has meant that a variation in a supply voltage level has a narrower voltage difference window than previously allowed. This scaling down has also meant less predictability of transistor-threshold voltage, meaning that variation in power-on reset circuit trip points may be large compared with a supply voltage level, which presently is generally one volt or less. Building power-on reset circuits having sufficient precision may be too costly and may add significant complexity.
Accordingly, it would both desirable and useful to provide means for determining supply voltage level validity using a conventional power-on reset circuit.